Addressing EUV’s Greatest Challenges: Stochastic Defects and High NA Enablement
On DEMAND webinar
The sustained pursuit of high density in semiconductors for both logic and memory applications has seen the rapid adoption of EUV lithography in recent years. After decades of development, this technology has reached the mainstream as device manufacturers employ EUV for critical layer patterning for sub-7 nm nodes in logic, and more recently in DRAM. Innovation in defectivity mitigation strategies need to keep pace to maintain the scaling roadmap that EUV affords. In addition, the single-exposure resolution limit of current EUV systems is fast approaching, necessitating the need for high numerical aperture (NA) EUV and the technology ecosystem to support it.
In this webinar, we will discuss:
- The latest technology developments related to EUV implementation
- Mitigation strategies to address both stochastic defects as well as conventional sources of variability
- What is needed to enable high NA and the implications to the scaling roadmap
Following the presentation, you will have the opportunity to participate in a live Q&A session with our technology experts.
About the Presenter:
Dr. David Medeiros joined Entegris as a senior director of engineering in the office of the CTO in April of 2021, where he is driving an enterprise level strategy on advanced patterning solutions with a focus on EUV.
Prior to joining Entegris, he spent six years at GLOBALFOUNDRIES, first as the senior director of patterning at Fab 8, and later as the vice president of central engineering. Prior to GF, he spent 17 years at IBM, culminating as the director of patterning R&D in the Microelectronics Division. His career began in the semiconductor industry as a synthetic chemist at Shipley Company.
Dr. Medeiros holds a PhD in chemistry from the University of Texas, Austin, and a BS in chemistry from the University of Massachusetts, Amherst.
