Introduction
We have reached an era in which a wide variety of computing applications are demanding a doubling of digital storage capacity every 1.5 years. Social media, video and photograph storage, memory sticks, storage centers, and data analytics are putting pressure on chip manufacturers to increase memory density. Demand fuels innovation, and the shift from 2D to 3D NAND storage is a clear example.
Multiple types of memory are available to satisfy various market demands. The memory pyramid (below) illustrates this well. At the top of the pyramid, the applications require fast embedded devices, while at the bottom the requirements demand less speed but require low cost. NAND memory resides in the middle below DRAM. In terms of requirements, NAND stands alone —it needs to be quite fast, but also low cost. The NAND architecture, which is read in strings of cells rather than individual cells, is most useful when storing large amounts of data such as video, photographs, and documents.
In the same way that population density is greater in high-rise buildings than in single story houses, the pressure to increase the number of bits stored in a given area resulted in a shift from 2D to 3D NAND storage during the past decade. From a device fabrication point of view, this replaced the challenges of shrinking device dimensions with stacking challenges (Table 1). The transition to 3D NAND also allowed an important added benefit, which is the Gate All Around (GAA) geometry. This helps with the fundamental issue of shrinking gate size—running out of material to store sufficient charge. This paper highlights some of the new stacking related challenges and proposes solutions to allow designers to increase the number of layers in 3D NAND structures to 96 and beyond.
SCALING CHALLENGES
When scaling 3D NAND, moving beyond 96 layers to 128 and
| 2D (planar cell) major challenges |
3D (GAA) major challenges |
| Advanced lithography (technically and cost) | High aspect ratio etching (profile control, mask formation, and selectivity, etc.) |
| Not enough charge available to store multiple bits | High aspect ratio deposition (uniformity and quality in extreme geometries) |
| Cross talk between cells | Need to access cells in 3D (staircase structure required) |
| Uniformity of cell performance | - |
higher seems to be the breaking point where changes in materials and fabrication processes will be necessary to maintain yield and performance at an acceptable level. The high aspect ratio (HAR) of these devices poses two primary types of challenges:
- Achieving uniform material properties from the bottom to the top of the stack
- Keeping contamination low to avoid yield loss as the structure is built up
The uniformity challenge affects several aspects of the 3D NAND structure. If the composition and electrical properties of the silicon oxide (SiO2) and silicon nitride (Si3N4) layers vary from the bottom to the top, the device will not function as designed. Under- or overetching of the nitride layers is another yield-loss risk that becomes greater as the layers increase. Deposition and etch processes, therefore, need to be optimized for these HAR structures.
The more layers a 3D NAND device has, the more its performance can be constrained by electron mobility in the vertical silicon channel. As explained in the paper “Considerations for Improving 3D NAND Performance, Reliability, and Yield,” doping the silicon with germanium (Ge) increases electron mobility. The challenge, however, is achieving uniform distribution of Ge throughout the channel.
