3D NAND Solutions
Three-dimensional vertically-stacked memory architectures offer exponential gains in flash memory storage, but they also introduce fundamental new challenges at the device fabrication and integration level. These challenges affect all aspects of the flash memory product chain, from design to supply to material handling, manufacturing, and delivery. These challenges become more acute as architectures are pushed from 64 vertical layers to 96, 128, and beyond. We understand many of these challenges and have ideal solutions for them.
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Featured White Paper
Improve 3D NAND Performance
This paper takes a closer look at the unique challenges of 3D NAND design and manufacturing, and considerations for overcoming them.
What to Know About 3D NAND, The Future of Flash Memory
You might not know about 3D NAND yet, but you should. The tiered form of flash memory offers a cost-effective way to store all that data you need to run your plant. You should also be aware of the technical challenges.
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View how Entegris solutions can help you overcome 3D NAND manufacturing challenges. Runtime: 02:10
3D NAND CHALLENGES AND ENTEGRIS SOLUTIONS
Three-dimensional vertically-stacked memory architectures offer exponential gains in flash memory storage, but they also produce fundamental new challenges at the device fabrication and integration level. These challenges affect all aspects of the flash memory production chain, from design to supply to material handling, manufacturing, and delivery.
These challenges become more acute as architectures are pushed from 64 vertical layers to 96, 128, and beyond.
We understand many of these challenges and have ideal solutions for them.
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3D NAND Solutions
Pictorial of 3D NAND manufacturing challenges and Entegris solutions for overcoming them.
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Decades-old practices are no longer effective when increasing the number of 3D NAND structures to 96 layers and beyond.
Contamination and purity challenges can be tackled by changing how deposition and etch tools are coated while integrating new chemistries in deposition and etching steps can alleviate vertical scaling challenges.
Product Solutions
Material Purity and Performance
Process purity and defect controls are critical in 3D NAND processes. The overall complexity of 3D NAND design and manufacturing adds to the challenges fabs are facing with contamination control. Every generation of 3D NAND is becoming more sensitive to contamination. Material purity is more critical because defects have a greater impact. As the number of transistors increases in the stack, one defect can block more than one cell and kill the entire device more easily. Our Purasol™ SP/SN solvent purifier, Microgard™ filters, and Oktolex™ Impact® 8G photochemical filter solutions target particle, gel, and metals removal to reduce electrical failures in photolithography applications, helping make processes purer. It is common for atomic layer deposition (ALD) chemical precursors to be carbon-containing molecules. Given a large stack of memory cells (96 layers or more) the residence time of carbon-containing by-products can be longer at the bottom compared to the top, which can lead to deposition thickness differences. Talk to us about carbon-free precursors and precursor delivery systems such as ProE-Vap® delivery system, which delivers adequate flux and high precursor utilization with minimal waste.
Deep Etch Structures
For deep etch structures, very thick layers of higher-viscosity photoresist (~1000 cps) are needed to define the amorphous carbon hard mask layers. This level of viscosity can cause microbubble formation during resist dispense that translates to defects during subsequent patterning. 3D NAND processes are more sensitive to lithographic defects because the dimensions are smaller (e.g., channel diameter is ~50 nm). Minimizing the bubbles requires a novel way to pump high-viscosity photoresist. We provide IntelliGen® two-stage pumps with Impact® filters for filtration, bubble removal, and consistent high-viscosity photoresist dispense. Additionally, our liner-based photoresist dispense systems, including NOWPak® canister systems and PDMPak® and NOWPak bottle systems, dispense high-viscosity photoresist accurately without bubbles or contamination.
Consistency Top to Bottom
As multilayer stack heights increase, so does the difficulty in achieving consistent etch and deposition profiles at the top and the bottom of the memory array. For example, given a ratio of ~100:1, the selective removal of Si3N4 in the memory stack becomes a wet-etch challenge. The difficulty is removing the Si3N4 consistently at the top and bottom of the stack and across the wafer, without etching any of the SiO2. Below 96 layers, this task is performed using hot phosphoric acid (~160°C); however, at 96 layers and above, a specially formulated wet etch chemistry is needed. We can provide these formulated chemistries to improve process margins.
Avoiding Queue-time Defects
Considering the vast number of deep channel holes (>2 billion per chip) and the stack thickness, the volume of by-products generated during the high-aspect ratio (HAR) etching step becomes more significant with each 3D NAND generation. Given the long process steps, a batch of wafers typically spends extended time in a front-opening unified pod (FOUP) where by-products can be adsorbed onto the inside FOUP surfaces and can be transferred to the wafer during queue time. To prevent by-product adsorption into the microenvironment, we offer an innovative Spectra™ EBM FOUP with diffuser purge, which uses a special polymer material with a moisture barrier that enables by-products to be pumped away more efficiently, resulting in fewer queue-time defects.